The present invention relates to a semiconductor device, and more specifically, to a method of fabricating a metal oxide semiconductor field effect transistor (MOSFET).
Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in the semiconductor technologies. Device dimensions are continuously scaled down to achieve high-performance CMOS ULSIs (Ultra-Large Scale Integrations). For such scaled devices, however, parasitics such as RC delay and source/drain series resistance easily degrade the circuit performance. As suggested in the reference by M. T. Takagi, et al., in IEDM Tech. Dig. p. 455, 1996, the degration factor of propagation delay on a gate electrode is a strong function of both channel width and gate electrode sheet resistance. Thus, the finite value of gate electrode sheet resistance limits the maximum channel width which can be used in ULSIs.
The Self-Aligned Ti Silicide contact source/drain and gate (Ti salicide) process is one of the candidates for low gate electrode sheet resistance and low source/drain resistance. The ultra-short channel MOSFET with self-aligned silicide contact is required for high-speed circuit. However, as mentioned in the article by M. Ono, et al., in IEDM Tech. Dig., p. 119, 1993, it is difficult to define the gate length to be below 0.1 xcexcm due to the limitation of current optical lithography.
The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are formed in the substrate. A metal silicide contact is formed on the top surface of the gate structure, and on the surface of the source and drain regions. Extended source and drain regions are formed beneath the side-wall spacers and are connected next to the source and drain regions.
After growing a thin gate oxide film on silicon substrate, an undoped poly-Si or amorphous Si (xcex1-Si) film is deposited by the LPCVD system. Then, a thin nitride film and a n+ doped poly-Si film are deposited. The gate region is defined to etch back the n+ doped poly-Si film. A low temperature steam oxidation process is performed to oxidize the n+ doped poly-Si. At this step, the size of the n+ doped poly-Si film can be reduced to the range of nanometer dimensions. The thermal polyoxide film is removed by BOE or diluted HF solution and the residual doped poly-Si were used as a mask to etch cap nitride film. The residual n+ doped poly-Si and the cap nitride film are used as masks to etch undoped poly-Si to form an ultra-short channel gate. For a nMOSFET fabrication, CVD PSG film is deposited and then etched back to form PSG spacers. Similarily, for PMOSFET fabrication, a CVD BSG film is deposited and then etched back to form BSG spacers. The cap nitride film was removed and a noble metal was deposited on all areas. The source, drain, and gate are doped by a high dose arsenic or phosphorous implant through the noble (or refractory) metal. Finally, the two-step RTP annealing process is used to form self-aligned silicided (salicided) contact MOSFET.